In integrated circuits that comprise output stages for driving discrete power devices or themselves integrated on the same chip containing the control circuitry, it is common to use a bootstrap capacitor to ensure a correct powering of the driving stage. In these systems, it is essential that the bootstrap capacitor is charged in very short periods of time. This is usually attained through a diode emulator LDMOS transistor used to rapidly charge the bootstrap capacitor.
In the case of a driving circuit for a so-called High Side Driver (HSD) of a half-bridge output stage, the LDMOS transistor should be capable of charging the bootstrap capacitor when the HSD is referred to low voltage, that is, when its output is low. The LDMOS transistor should emulate a high impedance when the HSD is referred to high voltage, that is, when its output is high. These functioning conditions must also be ensured during the HSD switching phase from high to low voltage or vice versa. These conditions must also be ensured despite possible current injections caused by charging and discharging of the capacitances associated with the LDMOS integrated structure that must sustain the high voltage supply of the power device.
The publication WO 94/27370 discloses a half-bridge circuit comprising a driving module for the lower device and a driving floating module for the higher power device. The driving module for the higher transistor is realized in an isolated well region and a properly controlled LDMOS transistor emulates a high voltage charging diode of a bootstrap capacitor. In these cases it is necessary to control the effects of the parasite bipolar junction transistors associated with the LDMOS integrated structure.
The document EP-A-0743752, points out and describes certain conditions that originate problems tied to the switch-on of the parasitic transistors of the LDMOS integrated structure. The reference also describes different circuit layouts capable of averting current consumption caused by the switch-on of parasitic transistors of the LDMOS integrated structure, and to avoid the occurrence of conditions that may cause the destruction of the integrated device itself.
The above cited European patent application EP-A-0743752, is herein incorporated by way of direct reference. FIG. 1 highlights the protecting circuit described in the European patent application. According to the approach described in the European patent application, there exists a functioning phase of the integrated circuit, referred to as UVLO, when the voltage supply Vs is less than the minimum switch-on voltage of the entire integrated device including also the LDMOS transistor. During this time, with switches SW1 and SW2 both open, the potential of the body node VB of the LDMOS structure is kept at the circuit ground potential.
FIG. 1 shows that the LDMOS transistor is controlled through a bootstrap capacitor Cp charged by a diode D1 connected to the circuit supply node Vs, by an inverter IO1 driven by a Logic Control circuit as a function of a Low Gate Drive Signal and a second logic drive signal (UVLOb). This second logic drive signal is active during a phase wherein the supply voltage Vs is lower than the minimum switch-on voltage of the integrated device.
The protecting circuit as described in the European patent application herein reproduced in FIG. 1, while usually effective to prevent spurious switch-on, has a disadvantage of requiring to carry out such a function, that the current be such that the voltage drop on the R resistance is sufficient to switch-on the transistor Q1. This condition may not occur in some cases, for example, in quasi-static conditions or in the presence of leakage currents.
In fact, when the LDMOS transistor (LD) is OFF (node A linked to ground potential via the inverter IO1), its gate (G) represents a high impedance node.
This defines a particularly critical condition from the point of view of leakage currents entering the node G, or of possible charge injections on the same node G through the capacitive coupling between the gate-drain capacitance of the LDMOS transistor and the bootstrap capacitor Cp, as caused by steep fronts during high voltage switching. These charges that may be accidentally injected on the node G tend to increase the potential which, not being limited, could theoretically reach a voltage equal to Vs+Vz, where Vz is the breakdown voltage of the diode D1 that charges the bootstrap capacitor Cp.
In any case, it is sufficient that the voltage Vgs reaches a level of a few Volts to cause an undesired switch-on of the LDMOS transistor (LD), despite the existence of a switch-off logic signal on the output node A of the control inverter IO1. A similarly undue switch-on of the LDMOS transistor may take place in the switch-off phase, if the voltage Vs is taken to ground in a time span that would not allow the gate potential of the LDMOS transistor to follow the source voltage. The effect of an anomalous switch-on is a reverse current that may damage the integrated LDMOS transistor or, in any case, discharge the capacitance C charged by it.